SA56004X
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?NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 25 February 2013
16 of 43
NXP Semiconductors
SA56004X
Digital temperature sensor with overtemperature alarms
the Status register, at address 02h, during the interrupt service routine and then reset the
ALERT
mask bit 7 in the Configuration register to logic 0 at the end of the interrupt service
routine (see Figure 6
).
In order for the SA56004X to respond to the ARA command, the bit D0 in the ALERT
mode register must be set LOW.
ALERT
mask bit 7 and the ALERT mode bit D0 are both LOW for the POR default.
The following events summarize the ALERT
output interrupt operation in the SMBus Alert
mode:
Event A: Master senses the ALERT line being LOW.
Event A to B: Master sends a read command using the common 7-bit Alert Response
Address (ARA) of 0001100.
Event A to B: Alerting device(s) return ACK signal and their addresses using the
I
2
C-bus Arbitration (the device with the lowest address value sends its address first. The
master can repeat the alert reading process and work up through all the interrupts).
Event B: Upon the successful completion of returning address, the SA56004X resets its
ALERT
output (to OFF) and sets the ALERT
mask bit 7 in its configuration register.
Event C: Master should read the device status register to identify and correct the
conditions that caused the Alert interruption. The status register is reset.
Event D: Master resets the ALERT
mask bit 7 in the configuration register to enable the
device ALERT
output interruption.
Remark: The bit assignment of the returned data from the ARA reading is listed in
Table 17
. If none of the devices on the bus is alerted, then the returned data from ARA
reading is FFh (1111 1111).
Fig 6. ALERT
pin in SMBus Alert mode
temperature
002aad215
mote temperature high limit
remote diode temperature
ALERT pin
status register bit 4
(RHIGH)
A
B
D
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